Highlights
• Combined with IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithm software modules
• Ultra Precise Timing for 5G Radio Access Networks
• Four independent DPLL clock channels plus three additional DPLLs for NCO Hybrid, Split XO and redundant oscillator modes
• Five output synthesizers
• Any-to-any frequency conversion per channel
• Inputs: up to 10, differential or single-ended
• Outputs: up to 10 differential, up to 20 CMOS
• Output jitter 100 fs RMS typical for 156.25 MHz 12 kHz to 20 MHz
• Core power consumption <0.9W

Packet and/or physical-layer frequency, phase and time synchronization
• Physical-layer compliance with ITU-T G.8262, G.8262.1, G.813, G.812, Telcordia GR-1244, GR-253
• Packet-timing compliance with ITU-T G.8261, G.8263, G.8273.2 (class A,B,C,D), G.8273.4
• Enables 5G wireless applications with sub-100 ns time/phase alignment requirements
• Hitless reference switching

General Features
• Automatic self-configuration at power-up from internal Flash memory, 7 configurations
• Input-to-output alignment <100 ps
• Numerically controlled oscillator behavior in each DPLL and each synthesizer
• Easy-to-configure design requires no external VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
• SPI or I2C processor Interface
• 1.8V and 3.3V core VDD voltages
• Easy-to-use evaluation/programming software

The ZL30934A is a feature-rich network synchronization solution with up to seven independent DPLLs and five extremely low output jitter synthesizers combined with IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithm software modules. This solution is ideal for 5G Small Cell applications where Synchronous Ethernet (SyncE) and IEEE1588/PTP compliance is needed.

Another device in this family is ZL30833A which is targeted for 5G Small Cell SyncE timing applications. 

Click here for the list of supported IEEE 1588-2008 PTP Profiles and Equipment Clock Specifications.