Highlights
• Ultra Precise Timing for 5G Radio Access Networks
• Three independent DPLL clock channels plus three additional DPLLs for NCO Hybrid, Split XO and redundant oscillator modes
• Five output synthesizers
• Any-to-any frequency conversion per channel
• Inputs: up to 10, differential or single-ended
• Outputs: up to 10 differential, up to 20 CMOS
• Output jitter 100 fs RMS typical for 156.25 MHz 12 kHz to 20 MHz
• Core power consumption <0.9W

Physical-layer frequency synchronization
• Physical-layer compliance with ITU-T G.8262, G.8262.1, G.813, G.812, Telcordia GR-1244, GR-253
• Enables 5G wireless applications with sub-100 ns time/phase alignment requirements
• Hitless reference switching

General Features
• Automatic self-configuration at power-up from internal Flash memory, 7 configurations
• Input-to-output alignment <100 ps
• Numerically controlled oscillator behavior in each DPLL and each synthesizer
• Easy-to-configure design requires no external VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
• SPI or I2C processor Interface
• 1.8V and 3.3V core VDD voltages
• Easy-to-use evaluation/programming software

The ZL30633 is a feature-rich network synchronization solution with up to six independent DPLLs and five extremely low output jitter synthesizers. This solution is ideal for Synchronous Ethernet (SyncE) central timing applications such as routers, switches, optical transparent network and 4G/5G wireless base stations (CU/DU/RU).

We also have ZL3064x as line card jitter attenuators, such as ZL30642A, to form full SyncE&IEEE1588 Timing solution for any rack system.