• Two Independent APLL Channels
• Four Input Clocks Per Channel: One crystal/CMOS input, Two differential/CMOS inputs, One single-ended/CMOS input
• Any input frequency from 9.72MHz to 1250MHz (9.72MHz to 300MHz for CMOS)
• Clock selection by pin or register control
• Low-Jitter Fractional-N APLL and 3 Outputs Per Channel
• Any output frequency from <1Hz to 1035MHz
• High-resolution fractional frequency conversion with 0ppm error
• Each output has independent dividers
• Output jitter as low as 0.16ps RMS (12kHz-20MHz integration band)
• Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
• In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
• Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
• Precise output alignment circuitry and per-output phase adjustment
• Per-output enable/disable and glitch-less start/stop (stop high or low)
• Automatic self-configuration at power-up from internal EEPROM; up to four configs, pin-selectable
• SPI or I2C processor Interface
• Numerically controlled oscillator mode
• Spread-spectrum modulation mode

CREATE AND SAMPLE YOUR CUSTOM ZL30245 HERE

The ZL30245 is a flexible, high-performance, clock multiplier/generator. From any input clock frequency 9.72MHz to 1250MHz this device can produce frequency-locked output frequencies from less than 1Hz to 1035MHz and as many as 6 differential or 12 CMOS output clock signals. The ZL30245 has output jitter of 160fs RMS (12kHz to 20MHz). Automatic self-configuration from internal EEPROM allows clock signals to be available immediately after power-up or reset.