0
In Production
Type |
General Purpose |
Inputs |
1 |
CMOS Outputs |
9 |
Low-Jitter Synthesizers |
0 |
Typical Jitter (12kHz-20MHz) fs RMS |
<5000 |
Diff InputFreq. Range |
8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz |
Output Freq Range |
65.536 MHz |
The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.