0
SY100E222L
  • SY100E222L

SY100E222L

In Production

The SY100E222L is a low-skew, low-jitter device capable of receiving a high-speed LVECL/LVPECL input in either a single-ended or differential configuration. For single-ended configurations, a VBB output reference is supplied by the SY100E222L. A 2:1 input multiplexer selects from two differential input pairs by means of the CLK_SEL input select.The internal programmable divider for each of the four banks generates a ÷1 or ÷2 frequency of the selected input. The ÷1/÷2 divider outputs can be asynchronously synchronized with the master reset (MR) input so that the outputs will start out in a known state.The 15 total outputs are partitioned into four independently selected output banks in a 2/3/4/6 fanout configuration. Each of the four banks can independently selec...

Microchip Technology SY100E222L Product Info

16 April 2026 0

Parameters

Buffer Type

Fanout

Fanout

1:15

Icc (mA)

122

Input

LVECL/LVPECL

InputMux

No

Output Frequency (Max) (GHz)

1.5

MaxProp Delay (ps)

1520

MaxWithin Device Skew (ps)

50

No. of outputs

0

OE

0

Output

LVPECL

Supply Voltage

3.3

Features

    • Four programmable output banks and 15 total LVPECL-compatible differential outputs
    • Pin-compatible, plug-in replacement to MC100LVE222FA
    • fMAX clock = 1.5GHz
    • 50ps output-to-output skew
    • Four output banks with independent ÷1, ÷2 frequency control
    • 100k compatible I/O
    • Power supply 3.3V ±10%
    • –40°C to +85°C temperature range
    • Available in 52-pin LQFP package

Description

The SY100E222L is a low-skew, low-jitter device capable of receiving a high-speed LVECL/LVPECL input in either a single-ended or differential configuration. For single-ended configurations, a VBB output reference is supplied by the SY100E222L. A 2:1 input multiplexer selects from two differential input pairs by means of the CLK_SEL input select.The internal programmable divider for each of the four banks generates a ÷1 or ÷2 frequency of the selected input. The ÷1/÷2 divider outputs can be asynchronously synchronized with the master reset (MR) input so that the outputs will start out in a known state.The 15 total outputs are partitioned into four independently selected output banks in a 2/3/4/6 fanout configuration. Each of the four banks can independently select the ÷1 or ÷2 output frequency by means of the four separate frequency select pins (FSELA-FSELD) inputs.The SY100E222L is pin-for-pin compatible with the MC100LVE222FA device.The SY100E222L is part of a Micrel’s Precision Edge® product family. For other integrated clock divider plus fanout buffer options, consider Micrel’s SY89200 family.

Subscribe to Welllinkchips !
Your Name
* Email
Submit a request