• Serial Interface Architecture- Nibble-wide multiplexed I/O’s with SPI-like serial command structure: Mode 0 and Mode 3
• x1/x2/x4 Serial Peripheral Interface (SPI) Protocol and SQI protocol
• Burst Modes- Continuous linear burst, 8/16/32/64 Byte linear burst with wrap-around
• Page-Program- 256 Bytes per page in x1 or x4 mode
• Flexible Erase Capability- Uniform 4 KByte sectors, Four 8 KByte top and bottom parameter overlay blocks, One 32 KByte top and bottom overlay block, Uniform 64 KByte overlay blocks
• Software Write Protection- Individual Block-Locking: 64 KByte blocks, two 32 KByte blocks, and eight 8 KByte parameter blocks
• Low Power Consumption: Active Read current: 15 mA (typical @ 104 MHz), Standby Current: 15 µA (typical)
• Serial Flash Discoverable Parameters (SFDP)
• Industrial -40ºC to +85ºC and Extended -40ºC to +105ºC
• Packages Available: 8-contact WDFN (6mm x 5mm), 8-lead SOIC (208 mil), 16-lead SOIC (300 mil), 24-ball TBGA (6mm x 8mm)
• All devices are RoHS compliant
• Automotive Grade 2 and 3 available

The SST26VF064B Serial Quad I/O (SQI) flash device utilizes a 4-bit multiplexed I/O serial interface to boost performance while maintaining the compact form factor of standard serial flash devices. SST26VF064B also support full command-set compatibility to traditional Serial Peripheral Interface (SPI) protocol. Operating at frequencies reaching 104 MHz, the SST26VF064B enables minimum latency execute-in-place (XIP) capability without the need for code shadowing on an SRAM. The device’s high performance and reliability make it the ideal choice for Network Appliance, DSL and Cable Modems, Wireless Lan, Computing, Digital TV, Smart Meter, Server, Set Top Box, Automotive and other Industrial applications. Further benefits are achieved with SST’s proprietary, high-performance CMOS SuperFlash® technology, which significantly improves performance and reliability, and lowers power consumption for high bandwidth, compact designs.

The SST26VF064B default at power up is with WP# and HOLD pins enable and SIO2 and SIO3 pins disable allowing for SPI protocol operations without register configuration.
The SST26VF064BA default at power up with WP# and HOLD pins disable and SIO2 and SIO3 pins enable allowing for Quad I/O operations without register configuration.