Product
0
PL133-67
  • PL133-67

PL133-67

In Production

The PL133-67 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-67 accepts a reference clock input from DC to 150MHz and provides 6 outputs of the same frequency.The PL133-67 is offered in a TSSOP-16L package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC.The PL133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled....

Microchip Technology PL133-67 Product Info

16 April 2026 1

Parameters

Description

1:6

Input

LVCMOS

Output

LVCMOS

Supply Voltage

2.5/3.3

Max Freq (GHz)

0.15

Icc (mA)

30

Max Within Device Skew (ps)

250

OE

True

Input Mux

False

Number Of Outputs

0

Buffer Type

Fanout

Fanout

1:6

Max Prop Delay (ps)

9200

Features

    • 1:6 LVCMOS output fanout buffer for DC to150MHz
    • 8mA Output Drive Strength
    • Low power consumption for portable applications
    • Low input-output delay
    • Output-Output skew less than 250ps
    • Low Additive Phase Jitter of 60fs RMS
    • 2.5V to 3.3V ±10% operation
    • Operating temperature range from -40°C to 85°C
    • Available in 16-Pin SOP GREEN/RoHS package

Description

The PL133-67 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-67 accepts a reference clock input from DC to 150MHz and provides 6 outputs of the same frequency.The PL133-67 is offered in a TSSOP-16L package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC.The PL133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8