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PIC32CM5164JH00048
  • PIC32CM5164JH00048
  • PIC32CM5164JH00048

PIC32CM5164JH00048

In Production

The Microchip PIC32CM JH series of 5V Cortex M0+ devices is designed for applications that operate in noisy environments such as Automotive and Industrial. These products feature hardware for Functional Safety which include ECC with Fault Injection and mBIST as well as functionality for Secure Boot and can be paired with a Security IC for Security Applications. The PIC32CM JH offer a wide range of peripherals including CAN-FD, the Peripheral Touch Control with Driven Shield Plus (PTC,) Advanced Timer/Counters, and SERCOMs (USART, SPI, I2C, and LIN.) Supported by MPLAB X IDE, and MPLAB® Harmony....

Microchip Technology PIC32CM5164JH00048 Product Info

16 April 2026 0

Parameters

Part Family

PIC32CM JH

CPU Type

Cortex-M0+

MaxSpeed (MHz)

48

Program Memory Size (KB)

512

SRAM (KB)

64

Temp. Range Min.

-40

Temp. Range Max.

125

Operation Voltage Min.(V)

2.7

Operation Voltage Max.(V)

5.5

I2C

6

UART

6

QSPI

0

Crypto Engine

No

Internal Oscillator

32khz, 32Khz ULP, 48Mhz

Pin Count

48

Secure Subsystem

No

Secure Boot

Yes

Features

    Processor:
  • Arm® Cortex®-M0+
  • 48 MHz (2.46 CoreMark/MHz)
  • Single-cycle hardware multiplier
  • Nested Vector Interrupt Controller (NVIC)
  • Memory Protection Unit (MPU)
    Operating Voltage Range:
  • 2.7-5.5V
    Memory:
  • Up to 512 KB Flash
  • Up to 64 KB SRAM
  • 8 KB Data Flash Read While Write (RWW) section
    System:
  • 12-channel Direct Memory Access Controller (DMAC)
  • 12-channel Event System
  • 16 external interrupts (HW debounce) + 1 non-maskable interrupt
  • Hardware Divide and Square Root Accelerator (DIVAS)
  • Position Decoder (PDEC) working in quadrature, Hall or Counter mode
    Security and Safety:
  • Size-configurable immutable boot section in Flash for Secure Boot
  • ECC with fault injection for Flash, Data Flash and SRAM
  • CRC32 computation on SRAM, Flash and Data Flash sections through the Device Service Unit (DSU)
  • Memory Built-In Self-Test (MBIST) of SRAM
  • Integrity Check Module (ICM) to monitor memories based on secure hash algorithm (SHA1, SHA224, SHA256), DMA assisted
  • Clock failure Detection
    Enhanced Peripheral Touch Controller (PTC):
  • Driven Shield Plus for moisture tolerance and noise immunity
  • Up to 256 (16 x 16) mutual-capacitance channels
  • Up to 32 self-capacitance channels with Driven Shield Plus
  • Supports wake-up on touch from Standby Sleep mode
    Advanced Analog:
  • Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC)
  • 10-bit, 350 KSPS Digital-to-Analog Converter (DAC)
  • Analog Comparators (AC) with window compare function
    Additional Peripherals and Communications Interfaces:
  • Up to 2 Controller Area Network (CAN) Interfaces with support for CAN-FD
  • USART, I2C, LIN Host/Client, SPI, RS-485, PMBusTM, SMBusTM
  • 16-bit & 24-bit Timer Counter for Control (TCC)
  • 16-bit Timer Counters (TC)
  • Watchdog Timer (WDT) with Window Mode
  • 32-bit Real Time Counter (RTC) with Clock/Calendar Functions
    Development Support:
  • MPLAB X IDE
  • MPLAB Harmony v3 & MCC
  • Two-pin Serial Wire Debug (SWD) programming and debugging interface
  • Micro Trace Buffer (MTB) for Instruction Trace in SRAM

Description

The Microchip PIC32CM JH series of 5V Cortex M0+ devices is designed for applications that operate in noisy environments such as Automotive and Industrial. These products feature hardware for Functional Safety which include ECC with Fault Injection and mBIST as well as functionality for Secure Boot and can be paired with a Security IC for Security Applications. The PIC32CM JH offer a wide range of peripherals including CAN-FD, the Peripheral Touch Control with Driven Shield Plus (PTC,) Advanced Timer/Counters, and SERCOMs (USART, SPI, I2C, and LIN.) Supported by MPLAB X IDE, and MPLAB® Harmony.

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