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MPFS095TLS
  • MPFS095TLS
  • MPFS095TLS

MPFS095TLS

In Production

The PolarFire® SoC FPGA is built on the award-winning PolarFire FPGA architecture and is the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux and real-time applications. The family delivers up to 50% lower power than alternative FPGAs and spans from 23k to 461k logic elements and features 12.7G transceivers.

Microchip Technology MPFS095TLS Product Info

16 April 2026 0

Parameters

LogicElements(K)

93

Math Blocks 18x18

292

Fabric uPROM Kbit (kilobit)

387

Total RAM KB (kilobyte)

6700

PCIe Lanes

2

SERDES_Speed Gbps (gigabits per second)

12.7

SERDES lanes

4

PLLs

8

Temp Max °C (degrees Celsius)

100

Temp Min °C (degrees Celsius)

-40

Max. User I/O

412

Features

    FPGA Fabric
  • 93K logic elements (4-input LUT + DFF)
  • 292 Math blocks (18x18 MACC)
  • 4 SerDes lanes of 12.7 Gbps
    Microprocessor Subsystem
    Processor
  • 1x 64-bit RV64IMAC monitor/boot core
  • 4x 64-bit RV64GC Application cores
  • Fmax of 667 MHz (–40 °C to 100 °C Tj),
  • 3.125 CoreMarks/MHz, 1.714 DMIPS/MHz
    Storage
  • MMC 5.1 SD/SDIO
  • 1 Quad SPI flash controller
  • 128 KB eNVM
  • 56KB sNVM
    Memory Interfaces
  • 36-bit DDR4/DDR3/LPDDR4/LPDDR3 memory controller with SECDED
    Communication Interfaces
  • 2x GigE MACs, USB 2.0 OTG, 5x multi-mode UARTs, 2x SPI, 2x I2C, 2x CAN 2.0 Controllers.
  • 2x PCIe Gen2 End Points/Root Ports

Description

The PolarFire® SoC FPGA is built on the award-winning PolarFire FPGA architecture and is the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux and real-time applications. The family delivers up to 50% lower power than alternative FPGAs and spans from 23k to 461k logic elements and features 12.7G transceivers.

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