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MPF050TL
  • MPF050TL

MPF050TL

In Production

PolarFire FPGAs deliver the industry’s lowest power at mid-range densities with exceptional security and reliability. Features 12.7G transceivers and offers up to 50% lower power than competing mid-range FPGAs. The devices are ideal for a wide range of applications within wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industrial automation and IoT markets. Lower Power "L" Devices • Provide up to 35 percent lower static power with identical electrical specificationsCost-optimized Architecture• Transceiver performance optimized for 12.7 Gbps, which yields smaller size• 1.6 Gbps I/Os supporting DDR4/DDR3/LPDDR3, LVDS - hardened I/O gearing logic with CDR (supports SGMII/GbE links on GPIOs)• Best-in-class...

Microchip Technology MPF050TL Product Info

16 April 2026 1

Parameters

LogicElements(K)

48

Math Blocks 18x18

150

Fabric uPROM Kbit (kilobit)

216

Total RAM Kbit (kilobit)

3600

PCIe Lanes

2

SERDES_Speed Gbps (gigabits per second)

12.7

SERDES lanes

4

PLLs

8

Temp Min °C (degrees Celsius)

-40

Temp Max °C (degrees Celsius)

100

Max. User I/O

188

Features

  • 48K logic elements
  • 150 Math blocks (18x18 MACC)
  • Total RAM 3.6 Mbits
  • uPROM 216 Kbits
  • DLL/PLL 8
  • 4 SERDES lanes
  • 2 PCIe Endpoints / Root ports
  • 176 User I/O
  • Description

    PolarFire FPGAs deliver the industry’s lowest power at mid-range densities with exceptional security and reliability. Features 12.7G transceivers and offers up to 50% lower power than competing mid-range FPGAs. The devices are ideal for a wide range of applications within wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industrial automation and IoT markets.


    Lower Power "L" Devices

    • Provide up to 35 percent lower static power with identical electrical specifications

    Cost-optimized Architecture

    • Transceiver performance optimized for 12.7 Gbps, which yields smaller size

    • 1.6 Gbps I/Os supporting DDR4/DDR3/LPDDR3, LVDS - hardened I/O gearing logic with CDR (supports SGMII/GbE links on GPIOs)

    • Best-in-class high-performance, hardened security IP in mid-range devices

    Power Optimization

    • The lowest static power—1/10 static power vs. competing devices

    • Transceiver optimized for 12.7 Gbps, which yields 1/2 the power vs. competing devices

    • Integrated hard IP—DDR PHY, PCIe endpoint/root port, crypto processor

    • Total power (static and dynamic)—up to 50% lower power

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