• Six Simultaneous Sampling 24-bit Delta-Sigma ADCs
• 94.5 dB SINAD, -107 dBc Total Harmonic Distortion (THD) (up to 35th Harmonic), 112 dBFS SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement Error over a 10,000:1 Dynamic Range
• Advanced Security Features: - 16-bit Cyclic Redundancy Check (CRC) checksum - 16-bit CRC checksum and interrupt alert for register map configuration - Register map lock with 8-bit secure key
• Programmable Data Rate up to 125 ksps
• Oversampling Ratio up to 4096
• Ultra-Low Power Shutdown Mode with < 10 µA
• -122 dB Crosstalk between Channels
• Differential Voltage Reference Input Pins
• High Gain Programmable-Gain Amplifier (PGA) on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time Resolution
• Separate Data Ready Pin for Easy Synchronization
• Individual 24-bit Digital Offset and Gain Error Correction for Each Channel
• High-Speed 20 MHz Serial Peripheral Interface (SPI) with Mode 0,0 and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum Communication Time
• Available in a 28-lead SSOP and 40-lead UQFN Package
• AEC-Q100 Grade 1

The MCP3913 errata has been addressed with a silicon change resulting in an update to the part number (MCP3913B). Although there are no plans to discontinue the MCP3912, new designs would be best served by using the newer device. The MCP3912B is particularly a better choice for systems sensitive to power consumption, as a circuit level resolution to one of the errata has been rendered unnecessary.

We welcome questions, comments and recommendations for improvements to this page - please contact us at: ADCwebrequests@microchip.com if you have any; please mention the part number in the email subject header.