Input Clocks
• One Crystal Input
• Three Differential or CMOS/TTL Inputs
• Differential to 750MHz, CMOS/TTL to 125MHz
• Continuous Input Clock Quality Monitoring
• Automatic or Manual Clock Selection
• Glitchless Reference Switching

Low-Bandwidth DPLL
• Features Suitable for General-Purpose Jitter Attenuation
• Programmable Bandwidth, 4Hz to 400Hz
• Attenuates Jitter up to Several UI
• Glitchless Reference Switching
• Manual Phase Adjustment

Two APLLs Plus 5 Output Clocks
• APLLs Perform High Resolution Fractional-N Clock Multiplication
• Any Output Frequency from <1Hz to 750MHz
• Each Output Has an Independent Divider
• Output Jitter 0.18 to 0.3ps RMS for APLL-only Integer Multiply and 0.25 to 0.4ps RMS for Other modes (12kHz to 20MHz)
• Outputs are CML or 2xCMOS, Can Interface to LVDS, LVPECL, CMOS, HSTL, SSTL and HCSL
• CMOS Output Voltage from 1.5V to 3.3V

General Features
• Automatic Self-Configuration at Power-Up from External EEPROM Memory
• Uses External Crystal, Oscillator or Clock Signal As Master Clock
• Internal Compensation for Local Oscillator Frequency Error
• SPI Processor Interface
• 1.8V + 3.3V Operation (5V Tolerant)
• -40 to +85°C Operating Temp. Range
• 10mm x 10mm CSBGA Package

The MAX24605 is a flexible, high-performance clock multiplier and jitter attenuator ICs that include a DPLL and two independent APLLs. When locked to one of two input clock signals, the device performs any-to-any frequency conversion. From any input clock frequency 2kHz to 750MHz the devices can produce frequency-locked APLL output frequencies up to 750MHz and as many as 5 output clock signals that are integer divisors of the APLL frequencies. Input jitter can be attenuated by an internal low-bandwidth DPLL. The DPLL also provides glitchless switching between input clocks and numerically controlled oscillator capability. Input switching can be manual or automatic. Using only a low-cost crystal or oscillator, the device can also serve as frequency synthesizer IC. Output jitter is typically 0.18 to 0.3ps RMS for an APLL-only integer multiply and 0.25 to 0.4ps RMS for APLL-only fractional multiply or DPLL+APLL operation.