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HV7620
  • HV7620

HV7620

In Production

The HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. The device has 4 parallel 8-bit shift registers permitting data rates four times the speed of one. The data is clocked in simultaneously on all four data inputs with a single clock. Data is shifted in on a low to high transition of the clock. The latches and control logic perform the output enable function. The DIR pin causes clockwise (CW) shifting of the data when connected to VDD1, and counterclockwise (CCW) shifting when connected to LVGND. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. Data...

Microchip Technology HV7620 Product Info

16 April 2026 0

Parameters

Type

Source-Sink

Output Channels

32

Vout Operating (V) - Transient

225

Vout Operating (V) - Sustained

200

Iout (mA) per Channel

±50

Output Structure

Half-Bridge

Input Structure

Serial

Minimum Data Clock (MHz)

10

General Description

Serial to parallel converter with latches, channel polarity select, and blanking

Package

64/PQFP

Features

    • HVCMOS® technology
    • 5.0V logic and 12V supply rail
    • Output voltage up to +200V
    • Low power level shifting
    • Source/sink current minimum 50mA
    • 40MHz equivalent data rate
    • Latched data outputs
    • Forward and reverse shifting options (DIR pin)
    • Chip select
    • Polarity function

Description

The HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. The device has 4 parallel 8-bit shift registers permitting data rates four times the speed of one. The data is clocked in simultaneously on all four data inputs with a single clock. Data is shifted in on a low to high transition of the clock. The latches and control logic perform the output enable function. The DIR pin causes clockwise (CW) shifting of the data when connected to VDD1, and counterclockwise (CCW) shifting when connected to LVGND. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. Data is stored in the latches when LE is low. The current source on the logic inputs provides active pull up when the input pins are open.

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