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HV6810
  • HV6810

HV6810

In Production

The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high, and is latched when the latch enable is low. When the blanking input is high, all of the outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80V and 25mA source-current capability. All inputs are compatible with CMOS levels....

Microchip Technology HV6810 Product Info

16 April 2026 0

Parameters

Type

Source-Sink

Output Channels

10

Vout Operating (V) - Transient

90

Vout Operating (V) - Sustained

80

Iout (mA) per Channel

-25, +0.1

Output Structure

Half-Bridge

Input Structure

Serial

Minimum Data Clock (MHz)

5

General Description

Serial to parallel converter with data latches and channel polarity select

Package

20/SOIC 300mil

Features

    • High Output Voltage 80V
    • High speed 5MHz @5.0VDD
    • Low power IBB = 0.1mA (all high)
    • Active pull down 100µA min @25OC
    • Output source current 25mA @60V VBB
    • Each device drives 10 lines
    • High-speed serially-shifted data input
    • 5.0V CMOS-compatible inputs
    • Latches on all driver outputs
    • Pin-compatible replacement for UCN5810A and TL4810A, TL4810B

Description

The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high, and is latched when the latch enable is low. When the blanking input is high, all of the outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80V and 25mA source-current capability. All inputs are compatible with CMOS levels.

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