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HV3418
  • HV3418

HV3418

In Production

The HV3418 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a printer driver for inkjet applications. It can also be used in any application requiring multiple output, high voltage, low current sourcing and sinking capabilities. The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the c...

Microchip Technology HV3418 Product Info

16 April 2026 0

Parameters

Type

Source-Sink

Output Channels

64

Vout Operating (V) - Transient

200

Vout Operating (V) - Sustained

180

Iout (mA) per Channel

±5.0

Output Structure

Half-Bridge

Input Structure

Serial

Minimum Data Clock (MHz)

6

General Description

Serial to parallel converter with latches, polarity, and blanking

Package

80/PQFP

Features

  • Processed with HVCMOS® technology
  • Output voltages to 180V
  • Low power level shifting
  • Shift register speed:
  • 6.0MHz @ VDD = 5.0V
  • 12MHz @ VDD = 12V
  • Latched data outputs
  • Output polarity and blanking
  • CMOS compatible inputs
  • Forward and reverse shifting options

Description

The HV3418 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a printer driver for inkjet applications. It can also be used in any application requiring multiple output, high voltage, low current sourcing and sinking capabilities. The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL(polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) is high. The data in the latch is stored during LE transition from high to low.

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