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HV2661
  • HV2661

HV2661

In Production

HV2661 is a low charge injection 24-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. Input data is shifted into a 24-bit shift register that can then be retained in a 24-bit latch. To reduce any possible clock feed through noise, the latch enable (LE) should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage ...

Microchip Technology HV2661 Product Info

16 April 2026 0

Parameters

Interface

Serial

Configuration

8x3:1 MUX w/8 states

Supply Voltage Vpp - Vnn (V)

200

Analog Signal Voltage (V)

180

Switch Current (A)

±1.3

Switch Resistance typ (Ω)

18

Output Bleed Resistors

No

Package

LQFP-48

Features

    • 24-channel high voltage analog switch
    • 3.3 or 5.0V CMOS input logic level
    • 3:1 MUX-deMUX with 8 states
    • 20MHz data shift clock frequency
    • HVCMOS technology for high performance
    • Very low quiescent power dissipation, 10µA
    • Low parasitic capacitance
    • DC to 50MHz analog signal frequency
    • -60dB typical OFF-isolation at 5.0MHz
    • CMOS logic circuitry for low power
    • Excellent noise immunity
    • Cascadable serial data register with latches
    • Flexible operating supply voltages

Description

HV2661 is a low charge injection 24-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. Input data is shifted into a 24-bit shift register that can then be retained in a 24-bit latch. To reduce any possible clock feed through noise, the latch enable (LE) should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V.

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