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ATmega64M1
  • ATmega64M1
  • ATmega64M1

ATmega64M1

In Production

The high-performance, low-power Microchip 8-bit AVR® RISC-based microcontroller combines 64 KB ISP Flash memory with read-while-write capabilities, 2 KB EEPROM, 4 KB SRAM, 27 general purpose I/O lines, 32 general purpose working registers, one motor power stage controller, two flexible timer/counters with compare modes and PWM, one UART with HW LIN, an 11-channel 10-bit A/D converter with two differential programmable gain input stages, a 10-bit D/A converter, a programmable watchdog timer with an internal individual oscillator, SPI serial port, an on-chip debug system, and four software selectable power saving modes. The device operates between 2.7-5.5 volts. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching one MIPS per MHz, bala...

Microchip Technology ATmega64M1 Product Info

16 April 2026 0

Parameters

Program Memory Size (KB)

64

RAM

4096

Data EEPROM (bytes)

2048

Pin Count

32

Operation Voltage Max.(V)

5.5

Operation Voltage Min.(V)

2.7

ADC Resolution Max

10

ADC Channels

11

Zero Cross Detect

False

Number of Comparators

4

SPI

1

I2C

0

Stand alone PWM

10

Low Power

No

Numerically Controlled Oscillator (NCO)

0

Data Signal Modulator (DSM)

0

Description

The high-performance, low-power Microchip 8-bit AVR® RISC-based microcontroller combines 64 KB ISP Flash memory with read-while-write capabilities, 2 KB EEPROM, 4 KB SRAM, 27 general purpose I/O lines, 32 general purpose working registers, one motor power stage controller, two flexible timer/counters with compare modes and PWM, one UART with HW LIN, an 11-channel 10-bit A/D converter with two differential programmable gain input stages, a 10-bit D/A converter, a programmable watchdog timer with an internal individual oscillator, SPI serial port, an on-chip debug system, and four software selectable power saving modes. The device operates between 2.7-5.5 volts.

By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching one MIPS per MHz, balancing power consumption and processing speed.

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