• ARM Cortex-M3 revision 2.0 running at up to 96 MHz
• Memory Protection Unit (MPU)
• Thumb®-2 instruction set
• 128 Kbytes Dual Plane embedded Flash, 128-bit wide access, memory accelerator, dual bank
• 36 Kbytes embedded SRAM
• 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
• Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash controller with 4 Kbytes RAM buffer and ECC
• External Bus Interface - 8 or 16 bits, 4 chip selects, 24-bit address
• Embedded voltage regulator for single-supply operation
• POR, BOD and Watchdog for safe reset
• Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock
• High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast device startup
• Slow Clock Internal RC oscillator as permanent clock for device clock in low power mode
• One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device
• 17 Peripheral DMA Controller (PDC) channels and 4-channel central DMA
• Sleep, Wait, and Backup modes, down to 1.65 μA in Backup mode with RTC, RTT, and GPBR
• 100-lead LQFP – 14 × 14 mm, pitch 0.5 mm
• 100-ball TFBGA – 9 × 9 mm, pitch 0.8 mm
• Industrial (-40° C to +85° C)
• USB 2.0 Device: 480 Mbps, 4-Kbyte FIFO, up to 7 bidirectional Endpoints, dedicated DMA
• 3 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester support) and one UART
• 2 TWI (I2C compatible)
• 1 Serial Perpheral Interface (SPI)
• 1 Synchronous Serial Controller (SSC) (I2S)
• 1 High Speed Multimedia Card Interface (HSMCI) (SDIO/SD/MMC)
• 3-channel 16-bit Timer/Counter (TC) for capture, compare and PWM
• 4-channel 16-bit PWM (PWMC)
• 32-bit Real-time Timer (RTT) and Real-time Clock (RTC) with calendar and alarm features
• 57 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination
• Three 32-bit Parallel Input/Output Controllers
• 4-channel 12-bit 1 msps ADC with differential input mode and programmable gain stage
• 4-channel 10-bit ADC
• Serial Wire/JTAG Debug Port(SWJ-DP)
• Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
• IEEE1149.1 JTAG Boundary-scan on all digital pins.
• ASF-Atmel software Framework – SAM software development framework
• Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
• DMA support, Interrupt handlers Driver support
• USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
• RTOS integration, FreeRTOS is a core component

Microchip's ARM®-based SAM3U2C is a member of the SAM3U family of flash microcontrollers based on the high-performance 32-bit ARM Cortex®-M3 RISC processor.

It operates at a maximum speed of 96MHz and features 128KB of flash memory and 32KB of SRAM.

The peripheral set includes a High Speed USB device and PHY at 480Mbps, high-speed multimedia card interface for SDIO/SD/MMC, a 16-bit external bus interface supporting NAND flash, three USARTs, TWI (I²C), four SPIs, I2S, four PWM timers, three 16-bit timers, RTC, 4x12-bit and four 10-bit ADC.

The architecture is designed to sustain high-speed data transfers. The multi-layer bus matrix, multiple SRAM banks, PDC, and DMA support parallel tasks and maximize data throughput.

The SAM3U1C operates from 1.62V to 3.6V and is available in 100-pin LQFP and BGA packages.