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AT90CAN32
  • AT90CAN32
  • AT90CAN32

AT90CAN32

In Production

The high-performance, low-power Microchip 8-bit AVR RISC-based microcontroller combines 128KB ISP flash memory with read-while-write capabilities, 1KB EEPROM, 2KB SRAM, 53 general purpose I/O lines, 32 general purpose working registers, CAN controller (V2.0A/V2.0B compliant), real time counter, four flexible timer/counters with compare modes and PWM, 2 USARTs, byte oriented two-wire serial interface, an 8-channel/10-bit A/D converter with optional differential input stage with programmable gain, programmable watchdog timer with internal oscillator, SPI serial port, JTAG (IEEE 1149.1 compliant) interface for on-chip debugging and programming, and five software selectable power saving modes. By executing powerful instructions in a single clock cycle, the device achieves throughputs approach...

Microchip Technology AT90CAN32 Product Info

16 April 2026 0

Parameters

Program Memory Size (KB)

32

RAM

2

Data EEPROM (bytes)

1024

Pin Count

64

Operation Voltage Max.(V)

5.5

Operation Voltage Min.(V)

2.7

ADC Resolution Max

10

ADC Channels

8

Zero Cross Detect

False

Number of Comparators

1

SPI

1

I2C

1

Stand alone PWM

7

Low Power

No

Numerically Controlled Oscillator (NCO)

0

Data Signal Modulator (DSM)

0

Description

The high-performance, low-power Microchip 8-bit AVR RISC-based microcontroller combines 128KB ISP flash memory with read-while-write capabilities, 1KB EEPROM, 2KB SRAM, 53 general purpose I/O lines, 32 general purpose working registers, CAN controller (V2.0A/V2.0B compliant), real time counter, four flexible timer/counters with compare modes and PWM, 2 USARTs, byte oriented two-wire serial interface, an 8-channel/10-bit A/D converter with optional differential input stage with programmable gain, programmable watchdog timer with internal oscillator, SPI serial port, JTAG (IEEE 1149.1 compliant) interface for on-chip debugging and programming, and five software selectable power saving modes.

By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz, balancing power consumption and processing speed.

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