0
S25HL512TDPBHI010
  • S25HL512TDPBHI010

S25HL512TDPBHI010

Active and preferred

The S25HL512TDPBHI010 is a 512 Mb SEMPER™ NOR Flash memory with 45-nm MIRRORBIT™ technology and Quad SPI interface, supporting up to 102 MBps DDR read speeds at 1.8 V or 3.0 V. It offers flexible sector architectures, ISO 26262 ASIL-B compliance, built-in ECC and CRC, and SafeBoot for functional safety. Endurance Flex enables high-endurance or long-retention partitions, with up to 1,280,000 program-erase cycles. AEC-Q100 qualified for automotive and industrial use.

Infineon Technologies S25HL512TDPBHI010 Product Info

16 April 2026 0

Parameters

Density

512 MBit

Family

HL-T

Interface Bandwidth

66 MByte/s

Interface Frequency (SDR/DDR) (MHz)

133 / 66

Interfaces

Quad SPI

Lead Ball Finish

Sn/Ag/Cu

Operating Temperature range

-40 °C to 85 °C

Operating Voltage range

2.7 V to 3.6 V

Operating Voltage

3 V

Peak Reflow Temp

260 °C

Planned to be available until at least

2037

Qualification

Industrial

Features

  • 45-nm MIRRORBIT™ stores 2 bits/cell
  • Uniform and hybrid sector architectures
  • 256/512-byte page programming buffer
  • 1024-byte OTP secure silicon array
  • Quad SPI up to 102 MBps (DDR, 102 MHz)
  • Dual SPI up to 41.5 MBps (SDR, 166 MHz)
  • SPI up to 21 MBps (SDR, 166 MHz)
  • Functional safety: ISO26262 ASIL B compliant
  • Endurance Flex: high-endurance/retention
  • Data integrity CRC and built-in ECC (SECDED)
  • SafeBoot for init failure/config corruption
  • Legacy and advanced sector protection

Description

  • High density, reliable storage in small
  • Flexible sectoring for varied application
  • Fast programming for efficient data handling
  • Secure OTP for device authentication
  • High-speed Quad/Dual SPI for rapid data
  • Industry-leading functional safety for
  • Partitioning optimizes endurance
  • Robust data integrity with CRC and ECC
  • SafeBoot ensures system recovery and uptime
  • Advanced protection prevents unauthorized
  • Instant boot accelerates system startup
  • Hardware reset enables reliable system

Subscribe to Welllinkchips !
Your Name
* Email
Submit a request