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S25FL512SDSBHI213
  • S25FL512SDSBHI213

S25FL512SDSBHI213

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The S25FL512SDSBHI213 is a 512 Mb SPI NOR flash memory using Infineon's 65 nm MIRRORBIT™ technology and Eclipse™ architecture for fast program and erase. It supports SPI Multi-I/O (x1, x2, x4) and DDR commands, with up to 80 MBps read rates in Quad DDR mode. Operating from 2.7 V to 3.6 V core and 1.65 V to 3.6 V I/O, it meets AEC-Q100 Grade 1 (-40°C to +125°C). Features include a 512-byte page buffer, 100,000 cycles, 20-year retention, and advanced sector protection.

Infineon Technologies S25FL512SDSBHI213 Product Info

16 April 2026 0

Parameters

Density

512 MBit

Family

FL-S

Interface Bandwidth

80 MByte/s

Interface Frequency (SDR/DDR) (MHz)

133 / 80

Interfaces

Quad SPI

Lead Ball Finish

Sn/Ag/Cu

Operating Temperature range

-40 °C to 85 °C

Operating Voltage range

2.7 V to 3.6 V

Operating Voltage

3 V

Peak Reflow Temp

260 °C

Planned to be available until at least

2035

Qualification

Industrial

Features

  • CMOS 3.0 V core with versatile I/O
  • SPI interface with multi I/O support
  • 512 Mb (64 MB) density
  • Supports SPI clock up to 133 MHz
  • Quad, dual, and DDR read commands
  • 512-byte page programming buffer
  • Automatic ECC with single bit correction
  • Uniform 256-KB sectors
  • 100,000 program-erase cycles minimum
  • 20-year data retention minimum
  • 1024-byte OTP secure region
  • Block and advanced sector protection

Description

  • Versatile I/O enables flexible system design
  • Multi I/O SPI boosts data throughput
  • High density supports large code/data storage
  • 133 MHz SPI enables fast data access
  • Quad/DDR read maximizes read speed
  • Large buffer speeds up programming
  • ECC improves data reliability
  • Uniform sectors simplify memory management
  • High endurance for long device lifetime
  • 20-year retention ensures data safety
  • OTP region adds security options
  • Advanced protection enhances data safety

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