0
Active and preferred
Architecture |
QDR-II+ |
Bank Switching |
N |
Burst Length (Words) |
4 |
Data Width |
x 18 |
Density |
72 MBit |
Device weight |
6152.8 mg |
ECC |
N |
Family |
QDR-II+ |
Frequency |
250 MHz |
Interfaces |
Parallel |
Lead Ball Finish |
Sn/Pb |
On-Die Termination |
N |
Operating Temperature range |
-55 °C to 125 °C |
Operating Voltage range |
1.7 V to 1.9 V |
Organization (X x Y) |
4Mb x 18 |
Peak Reflow Temp |
220 °C |
Planned to be available until at least |
2033 |
Qualification |
Military |
Read Latency (Cycles) |
2 |