ADRV9040

RECOMMENDED FOR NEW DESIGNS

8T8R SoC with DFE, 400 MHz iBW RF Transceiver

Analog Devices ADRV9040 Product Info

10 February 2026 5

Features

Eight differential transmitters (Tx)
Eight differential receivers (Rx)
Two differential observation receivers (ORx)
Tunable range: 600 MHz to 7125 MHz
Single-band and Multiband (N x 2T2R/4T4R) capability
Four individual band profiles within tunable range (band profiles define bandwidth and aggregate sampling rate of a channel)
ADRV9040BBPZ-WB supports DPD for 400 MHz iBW/OBW
Simplifying system thermal solution
- 13 W power consumption for all blocks enabled (use case is TDD 200 MHz instantaneous bandwidth and 200 MHz occupied bandwidth, with all blocks (DPD, CFR, and CDUC/CDDC) enabled)
- 125°C maximum junction temperature for intermittent operation, 110°C for continuous (operating lifetime impact at >110°C can be offset by operation at <110°C based on acceleration factors)

Fully integrated DFE (DPD, CDUC, CDDC, and CFR) engine that reduces FPGA resources and halves SERDES lane rate
- DPD adaptation engine for power amplifier linearization
- CDUC/CDDC—maximum eight component carriers (CCs) per each transmitter/receiver channel
Multistage CFR engine
Supports DTx (micro sleep) power saving mode in downlink
Supports JESD204B and JESD204C digital interface
Multichip phase synchronization for all local oscillator (LO) and baseband clocks
Dual fully integrated fractional-N RF synthesizers
Fully integrated clock synthesizer

Part details & applications

The ADRV9040 is a highly integrated, system on chip (SoC) radio frequency (RF) agile transceiver with integrated digital front end (DFE). The SoC contains eight transmitters, two observation receivers to monitor transmitter channels, eight receivers, integrated LO and clock synthesizers, and digital signal processing functions. The SoC meets the high radio performance and low power consumption demanded by cellular infrastructure applications including small cell base-station radios, macro 3G/4G/5G systems, and massive MIMO base stations.

The receiver and transmitter signal paths use a zero-IF (ZIF) architecture that provides wide bandwidth with dynamic range suitable for contiguous and non-contiguous multi-carrier base-station applications. The ZIF architecture has the benefits of low power plus RF frequency and bandwidth agility. The lack of aliases and out-of-band images eliminate anti-aliasing and image filters. This reduces both system size and cost, also making band independent solutions possible.

The device also includes two wide-bandwidth observation path receiver subsystems to monitor transmitter outputs. This SoC subsystem includes automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC), and digital filtering. GPIOs that provide an array of digital control options are also integrated.

Multi-band capability is enabled by additional LO dividers and wideband operation. This allows four individuals band profiles within the tunable range, so maximizing use case flexibility.

The SoC has fully integrated DFE functionality, which includes carrier digital up/down conversion (CDUC and CDDC), crest factor reduction (CFR), digital predistortion (DPD), closed-loop gain control (CLGC) and voltage standing wave ratio (VSWR) monitor.

The CDUC feature of the ADRV9040 filters and places individual component carriers within the band of interest. The CDD

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