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ADRF8850
  • ADRF8850
  • ADRF8850

ADRF8850

RECOMMENDED FOR NEW DESIGNS

Low Power 2.4 GHz wBMS Manager

Analog Devices ADRF8850 Product Info

10 February 2026 5

Features

  • Low power 2.4 GHz radio
  • RF frequency range: 2400 MHz to 2483.5 MHz ISM band
  • 1 Mbps and 2 Mbps data rate options
  • Transmit output power: –10 dBm to +12 dBm
  • On-chip temperature sensor
  • Auxiliary ADC with three input ports
  • Few external components required
  • On-chip LDO power
  • Integrated RF match
  • Integrated transmit and receive switch
  • Microcontroller with a memory protection unit (MPU)
  • Secure JTAG port supporting code download
  • Security
    • Hardware root of trust
    • Secure boot
    • Secure update with roll-back protection
    • Hardware accelerator supporting AES-128, AES-256, ECC-256, and SHA-256
    • True random number generator (TRNG)
  • Memory
    • SRAM with SECDED ECC
    • Flash with SECDED ECC
    • ROM with SECDED ECC
    • Antifuse OTP
  • SPI × 3
  • GPIO ports
  • UART × 2
  • General-purpose, wake-up, and watchdog timers
  • On-chip POR
  • Programmable CRC up to 32 bits
  • AEC-Q100 qualified for automotive applications

Part details & applications

The ADRF8800/ADRF8850 are low power, integrated systems on chip (SoC) that include a 2.4 GHz (industrial scientific medical) ISM band radio and an embedded microcontroller unit (MCU) subsystem.

The ADRF8800/ADRF8850 provide wireless communications between the battery cell monitoring chip and the battery management system (BMS) controller. In the wireless battery management system (wBMS), the ADRF8800 nodes reside at the battery cells and take sensor data from the battery cell monitors. The nodes send the data over the air to an ADRF8850 network manager, and the manager provides the data to the BMS controller. The ADRF8850 network manager configures the network of nodes and manages the communications protocol.

The embedded MCUs integrate static random access memory (SRAM), embedded flash memory, one-time programmable (OTP) memory, and an analog subsystem that provides clocking and reset.

The ADRF8800/ADRF8850 has a rich set of peripherals, including serial peripheral interface (SPI), general-purpose input and output (GPIOs) ports, universal asynchronous receiver/transmitter (UART), and Joint Test Action Group (JTAG) port, as well as an analog-to-digital converter (ADC) and temperature sensor.

The ADRF8800/ADRF8850 provide secure boot using software stored in read only memory (ROM) that authenticates the next boot stage using a hardware accelerated 256-bit elliptic curve cryptography (ECC-256) engine. Other hardware accelerated cryptographic features include the 128-bit advanced encryption standard (AES-128), 256-bit advanced encryption standard (AES-256), and Secure Hash Algorithm 256 (SHA-256). The ADRF8800/ADRF8850 have protected key storage with a root encrypted key generated on-chip that is only accessible to the on-chip hardware. The devices incorporate a true random number generator (TRNG) that is used to seed a National Institute of Standards an

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