ADAU1979

PRODUCTION

Quad Analog-to-Digital Converter (ADC)

Analog Devices ADAU1979 Product Info

10 February 2026 5

Features

Four 4.5 V rms (typical) differential inputs
On-chip phase-locked loop (PLL) for master clock
Low electromagnetic interference (EMI) design
109 dB (typical) analog-to-digital converter (ADC) dynamic range
Total harmonic distortion + noise (THD + N): −95 dB (typical)
Selectable digital high-pass filter
24-bit stereo ADC with 8 kHz to 192 kHz sample rates

Digital volume control with autoramp function
I²C/SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I²S, and TDM modes
Master and slave operation modes
40-lead LFCSP
Qualified for automotive applications

Part details & applications

The ADAU1979 incorporates four high performance, analog-to-digital converters (ADCs) with 4.5 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I²C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1979 uses only a single 3.3 V supply. The device internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system. The ADAU1979 is available in a 40-lead LFCSP package.

Note that throughout the data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant.

Applications

Automotive audio systems
Active noise cancellation systems

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