AD9988

RECOMMENDED FOR NEW DESIGNS

4T4R Direct RF Receiver and Transmitter

Analog Devices AD9988 Product Info

10 February 2026 5

Features

Flexible, reconfigurable radio common platform design

Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R)
RF DAC/RF ADC RF frequency range up to 7.5 GHz
On-chip PLL with multichip synchronization

External RF clock input option

Versatile digital features

Selectable interpolation and decimation filters
Configurable DDCs and DUCs

8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC)
8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC)
FDUCs and FDDCs are fully bypassable
2 independent 48-bit NCOs per DUC or DDC

Programmable 192-tap PFIR filter for receive equalization

Supports 4 different profile settings loaded via GPIO

Receive AGC support

Fast detect with low latency for fast AGC control

Signal monitor for slow AGC control
Dedicated AGC support pins
Transmit DPD support

Programmable delay and gain per transmit data path
Coarse DDC delay adjust for DPD observation path

Supports real or complex digital data (8-, 12-, or 16-bit)

Auxiliary features

ADC clock driver with selectable divide ratios
Power amplifier downstream protection circuitry
On-chip temperature

Part details & applications

The AD9988 is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The device supports four transmitter channels and four receiver channels with a 4T4R configuration. This product is well suited for four-antenna TDD transmitter applications, where the receiver path can be shared between receiver and observation modes. The GPIO pins can be configured and toggled to support different user modes, while phase coherency is maintained. The maximum radio channel bandwidth supported is 1.2 GHz in a 4T4R configuration and a sample resolution of 16 bits. The AD9988 features a 16-lane 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port that allows up to eight lanes per transmit/receive link, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct to RF radio applications.

APPLICATIONS

Wireless communications infrastructure
W-CDMA, LTE, LTE-A, massive multiple input multiple output (MIMO)
Point to point microwave, E-band, and 5G mmWave
Broadband communications systems
DOCSIS 3.0+ cable modem termination system (CMTS)
Communication test and measurement systems

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