Analog Devices AD9697 Product Info

• JESD204B (Subclass 1) coded serial digital outputs
  • Lane rates up to 16 Gbps
• 1.01 W total power at 1300 MSPS
• SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range)
• SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range)
• Noise density
  • −153.9 dBFS/Hz (1.59 V p-p input range)
  • −155.6 dBFS/Hz (2.04 V p-p input range)
• 0.95 V, 1.8 V, and 2.5 V supply operation
• No missing codes
• Internal ADC voltage reference
• Flexible input range
  • 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)
• 2 GHz usable analog input full power bandwidth
• Amplitude detect bits for efficient AGC implementation
• 4 integrated digital downconverters
  • 48-bit NCO
  • Programmable decimation rates
• Differential clock input
• SPI control
  • Integer clock divide by 2 and divide by 4
  • Flexible JESD204B lane configurations
• On-chip dithering to improve small signal linerarity

The AD9697 is a single, 14-bit, 1300 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The −3 dB bandwidth of the ADC input is 2 GHz. The AD9697 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/ output (GPIO) pins, or to use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9697 between the DDC modes is selectable via serial port interface (SPI)programmable profiles.

In addition to the DDC blocks, the AD9697 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In