AD9545

RECOMMENDED FOR NEW DESIGNS

Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner

Analog Devices AD9545 Product Info

10 February 2026 5

Features

Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references
Complies with ITU-T G.8262 and Telcordia GR-253
Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10⁻⁸)
Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
Programmable digital loop filter bandwidth: 10⁻⁴Hz to 1850Hz
2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution < 1.37 × 10⁻¹² Hz), suitable for IEEE 1588 Version 2 servo feedback in PTP applications
Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported

5 pairs of clock output pins with each pair usable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
2 differential or 4 single-ended input references
Crosspoint mux interconnects reference inputs to PLLs
Supports embedded (modulated) input/output clock signals
Fast DPLL locking modes
Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
External EEPROM support for autonomous initialization
Single 1.8 V power supply operation with internal regulation
Built in temperature monitor and alarm and temperature compensation for en

Part details & applications

The AD9545 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

The 10 clock outputs of the AD9545 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.

The AD9545 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

Note that throughout the data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.

APPLICATIONS

Global positioning system (GPS), PTP (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronization
Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations
Small base station clocking, including baseband and radio
Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
Cable infrastructures
Carrier Ethernet

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