Analog Devices AD6655 Product Info

• SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at 70 MHz at 150 MSPS
• SFDR = 80 dBc to 70 MHz at 150 MSPS
• 1.8 V analog supply operation
• 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply
• Integer 1-to-8 input clock divider
• Integrated dual-channel ADC
  • Sample rates up to 150 MSPS
  • IF sampling frequencies to 450 MHz
  • Internal ADC voltage reference
  • Integrated ADC sample-and-hold inputs
  • Flexible analog input range: 1 V p-p to 2 V p-p
  • ADC clock duty cycle stabilizer
  • 95 dB channel isolation/crosstalk
• Integrated wideband digital downconverter (DDC)
  • 32-bit complex, numerically controlled oscillator (NCO)
  • Decimating half-band filter and FIR filter
  • Supports real and complex output modes
• Fast attack/threshold detect bits
• Composite signal monitor
• Energy-saving power-down modes

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.

In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.

In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.

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